A semiconductor device in a prior art includes a cell portion, in which a semiconductor device such as a MOSFET (i.e., metal-oxide semiconductor field effect transistor) is formed. The cell portion of the device is disposed at the center of the device so that electric field concentration is dispersed by an outer periphery of the device. Thus, the withstand voltage of the device is increased. In the prior art, a floating field ring as a guard ring is used for the outer periphery of the device to relax the electric field concentration. The guard ring is composed of the end portion of the outer periphery of the device. The guard ring is formed in such a manner that an impurity is implanted from the surface of a semiconductor substrate of the device by an ion implantation method. Then, the implanted impurity is activated by a thermal diffusion method. This method for forming the guard ring is preferably used for a silicon based semiconductor device.
However, it is difficult to increase the withstand voltage of the silicon based semiconductor device. Therefore, a silicon carbide based semiconductor device has been studied to increase the withstand voltage of the device. The silicon carbide crystal has a wide band gap wider than the silicon crystal, a high melting point higher than the silicon crystal, a low dielectric constant, a high breakdown withstand voltage, a high thermal conductivity coefficient, and a high electron mobility. Therefore, it is considered that the performance of the silicon carbide based semiconductor device is higher than the silicon based semiconductor device.
In the prior art, a silicon carbide semiconductor device is disclosed, for example, in U.S. Pat. No. 5,233,215. The device is shown in FIG. 9. The device includes a silicon carbide semiconductor substrate J4. The substrate J4 is composed of an N− conductive type drift layer J1, a P conductive type layer J2 and an N+ conductive type layer J3, which are laminated in this order. Multiple trenches J5 are formed on the surface of the substrate J4 so that the trench J5 penetrates the P conductive type layer J2 and the N+ conductive type layer J3. In each trench J5, an oxide film J6 is formed so that the inner wall of the trench is covered with the oxide film J6. Then, a metal film J7 is formed on the surface of the oxide film J6. Thus, the trench J5 is embedded with the oxide film J6 and the metal film J7. Thus, the P conductive type layer J2 is divided into multiple portions by the trench J5 so that the guard ring is formed. At the utmost outer periphery of the device, a deep trench J8 is formed. The deep trench J8 is embedded with an oxide film J9 and a metal film J10.
In the above device, electric field generated from the N− conductive type drift layer J1 is concentrated at the oxide film J6 disposed in the trench J5. Since the withstand voltage of the oxide film J6 is lower than the silicon carbide crystal, the withstand voltage of the device is defined by the oxide film J6 so that the withstand voltage of the device is decreased.
Further, after the trenches J5, J8 are formed, an oxide film forming process and a metal film forming process are necessitated. Furthermore, the deep trench forming process for forming the deep trench J8 at the utmost outer periphery is necessitated. Therefore, a manufacturing method for manufacturing the silicon carbide semiconductor device becomes more complicated.